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Modeling of substrate noise impact on CMOS VCOs on a lightly-doped substrate

vrijdag, 24 februari, 2006 - 16:00
Campus: Brussels Humanities, Sciences & Engineering campus
D
2.01
Charlotte Soens
doctoraatsverdediging

Thanks to the aggressive downscaling of the transistor dimensions, an increasing amount of analog and
digital functionality can be placed on the same die. This allows a reduction of cost and power
consumption for many applications and has lead to the proliferation of single-chip radio
implementations. However, this low cost implementation is jeopardized by the problem of the crosstalk
from the digital to the analog circuits via the common substrate. When the noise generated by the
digital circuits is injected into the substrate it couples into the sensitive analog and RF circuits residing
on the same die and affects their performance. The subject of this PhD thesis is the investigation by
measurements and simulations and the modeling of the impact of substrate noise on the performance of
sensitive analog and RF circuits on a lightly-doped substrate. The substrate crosstalk problem is
exacerbated by the increasing clock frequencies in future deep submicron technologies. Moreover, the
time design teams have to design new products is getting shorter. Design teams have one chance to get
a product to the market; the product must work successfully the first time. Therefore, substrate noise
problems have to be identified and eliminated as early as possible in the product design flow. To this
end, feeding the engineering intuition about substrate noise coupling is critical. This need is answered
in this thesis.

Today’s approach to the reduction of substrate noise coupling and impact is limited to for example
frequency planning, the separation of noisy and sensitive blocks, and the application of isolation
techniques. Low noise techniques are applied to reduce the noise generated by digital circuits and
differential design and active noise cancellation techniques are applied in an effort to protect the
sensitive analog circuits. However, all these techniques are applied in an add hoc way based on
intuition, often by overdimensioning and without guarantee that the system will work. In other words,
there is a lack of systematic methods to solve substrate noise coupling problems.

The available simulation methods are incomplete and therefore fail to provide an accurate estimation of
the noise propagation and impact. In this thesis a circuit simulation methodology is developed taking
all the physical effects of the substrate noise propagation and impact mechanism into account. For
example, the crucial role of the on-chip interconnect parasitic resistance is modeled. The simulation
method is applied to accurately predict the impact of substrate noise signals on the power spectrum of
LC-tank VCOs. In addition, it is demonstrated how the simulation method allows to investigate the
impact via each node in the analog circuit separately and this way to determine and protect the most
sensitive nodes.

Considered the increasing problem complexity of today’s systems, an approach at a higher level of
abstraction becomes unavoidable. This requires the development of high-level models describing the
generation, propagation and impact of substrate noise. Several macromodeling techniques have been
described in literature for the prediction of the generated substrate noise. For the impact of substrate
noise however, very few models are found. This thesis proposes a high-level grey-box model
describing the impact of substrate noise signals on the power spectrum of LC tank VCOs. This model is
combined with a high-level model describing the noise generated by a digital modem to demonstrate its
validity in a real mixed-signal context. This way, the measured power of the spurious tones in the
output spectrum of a 3.5 GHz LC-tank VCO resulting from the impact of a 40 k gate digital modem, is
accurately predicted. Besides allowing fast and accurate prediction of the impact of substrate noise the
model provides insight in the impact mechanisms, crucial to solve the problem. The availability of
high-level impact models would also permit the inclusion of substrate noise coupling in the
system-level study early in the design flow. Finally, based on the proposed model, this work
demonstrates substrate noise impact reduction by well-understood design techniques, rather than by
conservative design or blind application of recipes.